1. Field of the Invention
The present invention relates to a metal-oxide-semiconductor field-effect device with integrated monochannel structure which comprises an inverter transistor of the enhancement mode operation type and an active load constituted by a load transistor.
2. Description of the Prior Art
For realizing a logic device of the aforementioned type or a simple inverter stage, it is known from prior art to use a load transistor, the source electrode of which and possibly the gate electrode are connected to the drain electrode of the inverter transistor. The structure of such a logic device comprises generally a n-type conductivity channel, to which reference shall be made in the following, in order to obtain, on one hand, a small propagation time because the mobility of the negative carriers or electrons in a n-type channel is greater than that of the positive carriers or holes in a p-type conductivity channel and, on the other hand, a relatively high scale integration.
When a voltage equal to the high level "1" is applied to the input terminal of the logic device or to the gate electrode terminal of the inverter transistor, the level of the output terminal of the device or the drain electrode terminal of the inverter transistor is low "0" when the load transistor and the inverter transistor are both turned-on. For a given integration technique, i.e. for a predetermined length of the transistor channels, the simultaneous turning-on takes place when the input terminal voltage of the logic device is greater than the threshold voltage of the inverter transistor.
The width L of the inverter transistor channel is very great relative to that of the load transistor. The result is that the propagation time of the inverter transistor, the channel of which is much wider, is smaller than that of the load transistor.
The switching speed of the logic device and the realization of a steep slope of its transfer function which is equal to the ratio of drain-source voltage and the gate-source voltage of the inverter transistor, are then determined by the propagation time of the load transistor the channel of which is less wide than that of the inverter transistor.
In order to achieve a short propagation time of the logic device, which amounts to providing a high drain-source current of the load transistor, it is necessary to constitute a load transistor having a very wide channel, which leads to a much greater channel width of the inverter transistor.
Thus, for an integrated MOS transistor circuit in which the drain region and the source region are on a first implantation plane of a substrate wafer and in which the gate region is on a second implantation plane separating by a thin insulating silicon dioxide layer below the first implantation plane, the integration degree of the logic devices each comprising an inverter MOS transistor decreases as the switching speed of the logic device increases.